.TH cec 1 "June 2006" "Columbia University" "Esterel Compiler"
.SH NAME
cec \- The Columbia Esterel Compiler
.SH SYNOPSIS
.PP
.B cec
[
.B \-\-pdg
|
.B \-\-lists
|
.B \-\-lists-goto
|
.B \-\-vm
|
.B \-\-blif
|
.B \-\-verilog
|
.B \-\-sm
]
[
.I options...
]
.IB file .strl
.PP
.B cec
[
.B \-\-blif
|
.B \-\-verilog
]
[
.I options...
]
.IB file .sm
.PP
.B cec
.B \-\-vm-only

.SH DESCRIPTION

The
.B cec
command invokes the compiler, translating Esterel source code (suffix
.B .strl
) into either a C program or a circuit representation in either the BLIF format accepted by the
.BR sis (1)
logic optimizer from Berkeley or the Verilog language.  In the most
basic form,
.IP
.B cec myfile.strl
.PP
compiles the Esterel source file
.B myfile.strl
into the C file
.BR myfile.c .
A gate-level logic circuit, in the form of a BLIF file named
.B myfile.blif
can be generated by providing an option:
.IP
.B cec \-\-blif myfile.strl
.PP
Similarly, a Verilog file named
.B myfile.v
may also be generated:
.IP
.B cec \-\-verilog myfile.strl
.PP
In circuit-generation mode, all local state machines are given a
default encoding that can be manually overriden by supplying a
.B .sm
file.  This is done
by asking
.B cec
to generate an
.B .sm
file, editing it, then asking
.B cec
to finish its job, e.g.,
.IP
.B cec \-\-sm myfile.strl
.IP
.I Edit the file
.B myfile.sm
.IP
.B cec \-\-blif myfile.sm
.PP
This generates a
.B .blif
file.  Verilog may also be generated:
.IP
.B cec \-\-verilog myfile.sm
.SH OPTIONS
.PP
.I Output language options
.IP \fB\-\-pdg\fP
Generate a
.B .c
file generated with program dependence graphs.  This is the default.
.IP \fB\-\-lists\fP
Generate a
.B .c
file generated with dynamic lists.  This is generally less efficient
than the
.B \-\-pdg
option, although it may be superior on very parallel programs.
.IP \fB\-\-lists-goto\fP
Generate a
.B .c
file generated with dynamic lists that uses GCC's computed-goto
extension.  The generated code may be slightly faster than
.B \-\-lists-goto
option, but is less portable.
.IP \fB\-\-vm\fP
Generate a
.B .c
file built around a virtual machine.  The generated code is generally
much slower, but much smaller than that from the other C code generators.
.IP \fB\-\-blif\fP
Generate a
.B .blif
file as output.
.IP \fB\-\-verilog\fP
Generate a
.B .v
(Verilog) file as output.
.IP \fB\-\-sm\fP
Generate a
.B .sm
(state machine) file as output.  This file may be edited and later
resupplied to
.B cec
to complete the compilation process and produce either Verilog or
BLIF.
.IP \fB\-\-vm-only\fP
Print source for the virtual machine (in C) to standard out.  This is
not necessary to compile the
.B .c
file generated by the
.B \-\-vm
option as that file automatically includes the output of this option.
.PP
.I Circuit-generation options
.IP \fB\-\-sis\fP
Invoke the
.BR sis (1)
logic synthesis system as part of the compilation process.  By
default, this runs the standard
.B script.rugged
optimization script, but this may be changed using the following
option.
.IP "\fB\-\-sis\-script\fI script\fP"
Specify the script invoked by
.BR sis (1)
during optimization.  This implies
.B \-\-sis
.IP "\fB\-\-pdgblifargs\fI args\fP"
Specify additional arguments to be passed directly to the
.B pdgblif
pass.  Useful mostly to developers.
.IP \fB\-s\fP
Do not do the usual schziophrenic expansion.  This experimental option
may cause your program to fail.  Not recommended.
.PP
.I Output control options
.IP "\fB\-B\fI basename\fP"
Specify the basename of generated files.  This normally defaults to
the basename of the given
.B .strl
file, but may be specified explicitly using this option.
.IP "\fB\-D\fI directory\fP"
Specify the destination directory for generated files.  This defaults
to the current working directory.
.IP \fB\-K\fP
Keep all intermediate files; by default all are deleted after
compilation is complete.  Most are in XML format.  This is useful
mostly to developers.
.IP "\fB\-\-keep\fI extension\fP"
Keep the intermediate file with the given extension.  Invoking
.B cec \-\-keep
alone lists the possible extensions.  Multiple
.B \-\-keep
directives may be issued.
.PP
.I Miscellaneous options
.IP \fB\-h\fP
.IP \fB\-\-help\fP
Print a usage summary.
.IP \fB\-\-version\fP
Print the version of the compiler.
.IP \fB\-v\fP
.IP \fB\-\-verbose\fP
Enable verbose mode.  Report each internal command as it is executed.
.IP "\fB\-\-logfile\fI file\fP"
Generate a log file with the given name.  This contains version
information, the command line that invoked the compiler, and the list
of commands invoked during the compilation process.
.IP "\fB\-\-eachcmd\fI cmd\fP"
Specify a command to precede each command invoked by the compiler.
For example,
.B \-\-eachcmd time
times each internally-executed command.  Useful mostly to developers.
.SH BUGS
.PP
.B Cec
does not support certain parts of the Esterel V5 language,
including
the
.I pre
operator and tasks.  In addition, circuit generation mode does not
support variables, external types, functions, and procedures.
.PP
The generated circuit can always be improved.
.PP
The virtual machine has substantial limitations (e.g., 256 registers)
that prevent it from being used for large programs.
.SH AUTHORS
.IP \(em
Stephen A. Edwards (sedwards@cs.columbia.edu)
.IP \(em
Cristian Soviani (soviani@cs.columbia.edu)
.IP \(em
Jia Zeng (jia@cs.columbia.edu)
.SH SEE ALSO
.PP
.UR http://www.cs.columbia.edu/~sedwards/
<http://www.cs.columbia.edu/~sedwards/>
.UE
.PP
The CMA/INRIA Esterel V5 compiler, available from
.UR http://www.esterel-techologies.com/
<http://www.esterel\-techologies.com/>
.UE
.PP
.I The Esterel V5 Language Primer
.PP
Gerard Berry,
.I The Constructive Semantics of Esterel
.PP
The Icarus Verilog simulator/synthesizer
.UR http://www.icarus.com/eda/verilog/
<http://www.icarus.com/eda/verilog/>
.UE
.PP
The
.BR sis (1)
logic synthesis system.
.\" Local Variables:
.\" compile-command: "groff -Tps -man cec.1 > cec.1.ps"
.\" End:
